1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor devices configured with input/output (I/O) separation.
2. Description of the Background Art
In recent years there has been an increasing demand for rapid data transfer between a semiconductor memory device and a processor as the semiconductor memory device has been increasingly used in the field of graphics. An effective means to meet the demand is increasing the width of a data bus to thereby enhance data transfer rate. Furthermore, to enhance the operating frequency of the data bus, input and output buses that are separately provided, i.e., an I/O separation can often be adopted in a semiconductor memory device.
A dynamic random access memory (DRAM) with such I/O separation is disclosed, e.g., in Advanced Electronics I-9 Ultra LSI Memory, by Kiyoo Ito, Baihukan, Nov. 5, 1994, pp.165-167. The DRAM includes an input line pair, a write column select gate connected between the input line pair and a bit line pair, an output line pair, and a read column select gate connected between the output line pair and a bit line pair. The DRAM adopts direct sensing, directly detecting a potential difference appearing on a bit line pair to read data. As such, a pair of MOS transistors is connected between the read column select gate and a ground node. One transistor's gate is connected to one bit line and the other transistor's gate is connected to the other bit line.
In such a DRAM, data is read from a memory cell when the read column select gate turns on and simultaneously the pair of transistors sense the current potential difference on the bit line pair and the potential difference thus appears on the output line pair. In writing data into a memory cell, the write column select gate turns on and the current potential difference on the input line pair is transmitted to the bit line pair.
Such I/O separation is advantageous in readily providing an enhanced data transfer rate, since if data are randomly read and written the data read from memory cell and the data written to a memory cell will not collide with each other on a data bus.
In the DRAM, write and read columns are both selected via a common column select line and a read column select gate thus also turns on when data is written. To prevent such an erroneous read, the read sense transistor must be disconnected from the ground node. Accordingly, a transistor may be provided at an end of the memory cell array to connect to the ground node a single common line crossing multiple bit line pairs and connecting with all of the sources of the transistors.
However, the common line, connected to the ground node only at an end of the memory cell array, has a relatively high impedance. As such, when a large number of read sense transistors simultaneously operate, the common line has a potential floating above the ground potential, disadvantageously resulting in a significantly reduced current driving capability of the transistors.
Furthermore, since not only the write column select gate but also a read column select gate are turned on in writing data, even with the common line disconnected from the ground node the read sense transistor also slightly turns on, disadvantageously resulting in an erroneous read.
While such disadvantages are not so serious for a DRAM with a narrow bandwidth, they cannot be ignored for a bandwidth increased to achieve rapid data transfer.